1. Field of the Invention
The present invention is generally in the field of semiconductors. More specifically, the present invention is in the field of fabrication of semiconductor devices.
2. Background Art
Due to its numerous advantages, such as high density, low power consumption, and relative noise immunity, for example, complementary metal-oxide-semiconductor (CMOS) technology is widely used in integrated circuits (ICs) to provide control logic and to mediate input/output (IO) for modern electronic systems. As advancements in process technologies have resulted in core and IO devices being scaled down, the operating voltages of those devices have been correspondingly reduced. Consequently, the design of circuits to interface higher voltage operating devices with circuits containing core and IO devices has become increasingly challenging.
The conventional design techniques for interfacing IO circuits with higher voltage devices used in earlier technology regimes, such as stacking devices, level translation, and the like, are proving to be inadequate in the face of continued reductions in core and IO operating voltages. Alternatives to the use of conventional interfacing techniques include separate design of some of the IO circuits using a high voltage process, or the use of additional processing and masking steps to accommodate interface with higher voltage devices. Unfortunately, neither alternative is desirable because both approaches render integration of high voltage devices with standard CMOS processing inefficient and costly.
Thus, there is a need to overcome the drawbacks and deficiencies in the art by delivering a solution compatible with existing CMOS fabrication process flows, which enables concurrent fabrication of high voltage devices.